1. Field of the Invention
The present invention relates generally to the field of computer systems, and specifically, to data manipulation instructions for enhancing value and efficiency of parallel instructions.
2. Background Information
To improve the efficiency of multimedia applications, as well as other applications with similar characteristics, a Single Instruction, Multiple Data (SIMD) architecture has been implemented in computer systems to enable one instruction to operate on several operands simultaneously, rather than on a single operand. In particular, SIMD architectures take advantage of packing many data elements within one register or memory location. With parallel hardware execution, multiple operations can be performed on separate data elements with one instruction, resulting in a significant performance improvement.
In many graphics applications, specifically three-dimensional ("3D") graphics applications, there are manipulation of scenes that have objects such as triangles and polygons, which are rotated, scaled, etc. The range of numbers in, for example, a thirty-two-bit register is from 0 to 2.sup.32 -1. However, in many instances, the values of the objects may need to be represented by a floating-point number because a bigger number range is required or the number is not a whole number (e.g., due to introduction of angles). Therefore, these values must be converted to floating-point numbers and moved to the floating-point registers. Currently, to go from a SIMD packed integer data item to a SIMD packed floating-point data item, on the floating-point side (i.e., floating-point registers) of a processor, requires numerous instructions.
FIG. 1 illustrates a conventional technique of converting a SIMD packed integer data item to a SIMD packed floating-point data item. Referring to FIG. 1, a SIMD packed data item having integer data elements I1 and I2 are contained in a first floating-point register ("FR1"). The packed data item is transferred from FR1 to a first integer register ("IR1") on the integer side of the processor, in response to a first instruction (INST1). This is done because of the more robust instructions available on the integer side of the processor. Once on the integer side of the processor, the first data element I1 is placed in the lower order bits of a second integer register ("IR2") and the sign of I1 is extended in the higher order bits of IR2, in response to a second instruction (INST2). In response to a third instruction (INST3), IR1 is arithmetically shifted right from the higher order bits to the lower order bits, and the sign of I2 is shifted in the higher order bits.
In response to fourth and fifth instructions (INST4 and INST5), the data items contained in IR2 and IR1 are transferred to floating-point registers FR1 and FR2, respectively. The data items in FR1 and FR2 are now on the floating-point side of the processor. In response to sixth and seventh instructions (INST6 and INST7), the integer data items in FR1 and FR2 are converted to corresponding floating-point data items F1 and F2, in extended precision format (82 bits). The data items F1 and F2 are each represented by a mantissa (M1 and M2) and an exponent (E1 and E2). Responsive to eight and ninth instructions (INST8 and INST9), the data items F1 and F2 are stored in memory at locations A and A+1, respectively. The data items F1 and F2 are stored as single precision values (32 bits). In response to a tenth instruction (INST10), the data items stored in memory locations A and A+1 are loaded in FR1 (64 bits), providing a floating-point data item. As can be seen, the conversion of a SIMD packed integer to a SIMD packed float requires ten instructions, three of which are memory instructions. Memory instructions are very costly as compared to non-memory instructions. This conversion from SIMD packed integer to SIMD packed float may be required for thousands of data items in an application.
Accordingly, there is a need in the technology for a method and apparatus for reducing the number of instructions required to covert a SIMD packed integer to a SIMD packed float.